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0.18 , six layer metal CMOS process 1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O Up to 4,008 dedicated flip-flops Up to 55.3 K embedded RAM Bits Up to 313 I/O Up to 370 K system gates IEEE 1149.1 Boundary Scan Testing
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Multiple dedicated Low Skew Clock
Networks High drive input-only networks Quadrant-based segmentable clock networks User Programmable Phase Locked Loops
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Hardwired DSP building blocks with integrated Multiply, Add, and Accumulate Functions.
Compliant Low Power Capability
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The QuickLogic products come with secure ViaLink technology that protects intellectual property from design theft and reverse engineering. No external configuration memory needed; Instant-on at Power-up.
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Up to twenty-four 2,304 bit Dual Port High
Performance SRAM Blocks Up to 55,296 embedded RAM bits RAM/ROM/FIFO Wizard for automatic configuration Configurable and cascadable
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High performance I/O cell with Tco< 3 ns Programmable Slew Rate Control Programmable I/O Standards: LVTTL, LVCMOS, LVCMOS18, PCI,
PLL
Embedded RAM Blocks Embeded Computational Units
PLL
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Independent I/O Banks capable of
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supporting multiple standards in one device
I/O Register Configurations: Input,
PLL Embedded RAM Blocks PLL
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7DEOH (FOLSVH,, 3URGXFW )DPLO\ 0HPEHUV 4/ Max Gates Logic Array Logic Cells Max Flip-Flops Max I/O RAM Modules RAM Bits PLLs ECUs VQFP CSBGA (0.8 mm) Packages PQFP FBGA (0.8 mm) BGA (1.0 mm) 47,052 16 x 8 128 526 90 4 9,216 0 0 100 196 208 4/ 63,840 16 x 16 256 884 124 4 9,216 0 0 100 196 208 4/ 188,946 32 x 20 640 1,697 139 16 36,864 0 0 100 196 208 4/ 248,160 40 x 24 960 2,670 250 20 46,100 4 10 208 280 484 4/ 320,640 48 x 32 1,536 4,002 310 24 55,300 4 12 208 280 484
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The QuickWorks package provides the most complete ESP and FPGA software solution from design entry to logic synthesis, to place and route, and simulation. The package provides a solution for designers who use third party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other third-party tools for design entry, synthesis, or simulation.
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Eclipse-II is fabricated on a 0.18 , six layer metal CMOS process. The core voltage is 1.8 V Vcc supply and the I/Os are up to 3.3 V tolerant. The Eclipse-II product line is available in commercial, industrial, and military temperature grades.

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The Eclipse-II logic cell structure is presented in )LJXUH . This architectural feature addresses today's register-intensive designs.
7DEOH 3HUIRUPDQFH 6WDQGDUGV )XQFWLRQ Multiplexer Parity Tree Counter 'HVFULSWLRQ 16:1 24 36 16 bit 32 bit FIFO 128 x 32 256 x 16 128 x 64 Clock-to-Out System clock 6ORZHVW 6SHHG *UDGH 5 ns 6 ns 6 ns 250 MHz 250 MHz 155 MHz 155 MHz 155 MHz 4.5 ns 200 MHz )DVWHVW 6SHHG *UDGH 2.8 ns 3.4 ns 3.4 ns 450 MHz 450 MHz 280 MHz 280 MHz 280 MHz 2.5 ns 400 MHz
The Eclipse-II logic cell structure presented in )LJXUH is a dual register, multiplexor-based logic cell. It is designed for wide fan-in and multiple, simultaneous output funtions. Both registers share CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from a dedicated input.
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The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven twoto-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay.
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The Eclipse-II Product Family includes up to 24 dual-port 2,304-bit RAM modules for implementing RAM, ROM, and FIFO functions. Each module is user-configurable into four different block organizations and can be cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown in )LJXUH .
2,304-bit RAM Module
MODE[1:0] WA[9:0] WD[17:0] WE WCLK ASYNCRD RA[9:0] RD[17:0] RE RCLK
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The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using two "mode" pins, designers can configure each module into 128 x 18 (Mode 0), 256 x 9 (Mode 1), 512 x 4 (Mode 2), or 1024 x 2 blocks (Mode 3). The blocks are also easily cascadable to increase their effective width and/or depth (see )LJXUH ).
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WDATA WADDR
RAM Module (2,304 bits)
RDATA RADDR
WDATA
RAM Module (2,304 bits)
RDATA
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The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. A similar technique can be used to create depths greater than 512 words. In this case address signals higher than the ninth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals. The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with data from an external PROM (typically for ROM functions).
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Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively--these functions require high logic cell usage while garnering only moderate performance results. The Eclipse-II architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the Eclipse-II device can address various arithmetic functions efficiently. This approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in )LJXUH .
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RESET D S1 S2 S3 CIN SIGN1 SIGN2 00 01 3-1 mux 10 Q[16:0] 3-4 decoder C B A
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8-bit Multiplier
2-1 mux
16-bit Adder
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A[0:15] CLK B[0:15] 2-1 mux
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The Eclipse-II ECU blocks ( 7DEOH ) are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations.
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Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1 billion MACs/s when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic.
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The modes for the ECU block are dynamically re-programmable through the programmable logic.
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Multiply- Add (registered) Multiply - Accumulate Add (registered)
a. tPD, tSU and tCO do not include routing paths in/out of the ECU block. b. Internal feedback path in ECU restricts max clk frequency to 238 MHz. c. B [15:0] set to zero.
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Instead of requiring extra components, designers simply need to instantiate one of the preconfigured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used for cascading PLLs. PLLs achieve a very short clock-to-out time--generally less than 3 ns. This low clock-to-out time is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively making the clock tree delay zero.
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)LJXUH illustrates a QuickLogic PLL.
1st Quadrant 2nd Quadrant 3rd Quadrant FIN Frequency Divide _ .1 . . _2 . . _4 . + Filter vco PLL Bypass 4th Quadrant Clock Tree
Frequency Multiply . _ .1 . _2 . . _4 . FOUT
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Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in )LJXUH ) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter ()LJXUH ). The charge pump generates an error voltage to bring the VCO back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry. Fout represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained in 7DEOH ). This clock signal is meaningful only when the PLL is configured for external use; otherwise, it remains in high Z state. Most QuickLogic products contain four PLLs. The PLL presented in )LJXUH controls the clock tree in the fourth quadrant of its FPGA. QuickLogic PLLs compensate for the additional delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback path. For more specific information on the Phase Locked Loops, please refer to QuickLogic Application Note 58.
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QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency--7DEOH indicates the features of each mode.
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7DEOH 3// 0RGH )UHTXHQFLHV 3// 0RGHO PLL_HF PLL_LF PLL_MULT2HF PLL_MULT2LF PLL_DIV2HF PLL_DIV2LF PLL_MULT4 PLL_DIV4 2XWSXW )UHTXHQF\ Same as input Same as input 2x 2x 1/2x 1/2x 4x 1/4x ,QSXW )UHTXHQF\ 5DQJH 66 MHz-150 MHz 25 MHz-133 MHz 50 MHz-125 MHz 16 MHz-50 MHz 100 MHz-250 MHz 50 MHz-100 MHz 16 MHz-40 MHz 100 MHz-300 MHz 2XWSXW )UHTXHQF\ 5DQJH 66 MHz-150 MHz 25 MHz-133 MHz 100 MHz-250 MHz 32 MHz-100 MHz 50 MHz-125 MHz 25 MHz-50 MHz 64 MHz-160 MHz 25 MHz-75 MHz
The input frequency can range from 16 MHz to 300 MHz, while output frequency ranges from 25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output frequencies.
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7DEOH summarizes the key signals in QuickLogic's PLLs.
7DEOH 4XLFN/RJLF 3// 6LJQDOV 6LJQDO 1DPH PLLCLK_IN PLL_RESET Input clock signal Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. PLL output This signal selects whether the PLL will drive the internal clock network or be used off-chip. This is a static signal, not a dynamic signal. Tied to GND = outgoing signal drives internal gates. Tied to VCC = outgoing signal used off-chip. Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). Out from PLL to internal gates This signal can drive the internal gates after going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND. Out to off-chip This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must be tied to VCC. Active High Lock detection signal NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the RESET signal. 'HVFULSWLRQ
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Eclipse-II features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-directional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply with the specific I/O standard selected. For single ended I/O standards, VCCIO specifies the input tolerance and the output drive. For voltage referenced I/O standards (e.g SSTL), the voltage supplied to the INREF pins in each bank specifies the input switch point. For example, the VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V compliance. Eclipse-II can also support the LVDS and LVPECL I/O standards with the use of external resistors ( see 7DEOH ).
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As designs become more complex and requirements more stringent, several application-specific I/O standards have emerged for specific applications. I/O standards for processors, memories, and a variety of bus applications have become commonplace and a requirement for many systems. In addition, I/O timing has become a greater issue with specific requirements for setup, hold, clock to out, and switching times. Eclipse-II has addressed these new system requirements and now includes a completely new I/O cell which consists of programmable I/Os as well as a new cell structure consisting of three registers--Input, Output, and OE. Eclipse-II offers banks of programmable I/Os that address many of the bus standards that are popular today. As shown in )LJXUH each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one output multiplexers.
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The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown in )LJXUH , each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers. The select lines of the two-to-one multiplexers are static and must be connected to either Vcc or GND. For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. The comparator and multiplexor in the input path allows for native support of I/O standards with reference points offset from traditional ground. For output functions, I/O pins can receive combinatorial or registered data from the logic array. For combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For registered output operation, the array logic drives the D input of the output cell register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register does not need to drive the routing the length of the output path is also reduced. The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. The signal can also be either combinatorial
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or registered. This is identical to that of the flow for the output cell. For combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank. For registered control operation, the array logic drives the D input of the OE cell register which in turn drives the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/O's. The CLK and RESET signals share common lines, while the clock enables for each register can be independently controlled. I/O interface support is programmable on a per bank basis. The two larger Eclipse-II devices contain eight I/O banks.The two smaller Eclipse-II devices contain two I/O banks per device. )LJXUH illustrates the I/O bank configurations. Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and INREF can be shared within the same bank (e.g. PCI and LVTTL).
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INREF 0
VCCIO 1
INREF 1
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Embedded RAM Blocks Embeded Computational Units
PLL
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INREF 7
INREF 2
Fabric
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INREF 5
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Each I/O has programmable slew rate capability--the slew rate can be either fast or slow. The slower rate can be used to reduce the switching times of each I/O.

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A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the need for external pull down resistors for used I/Os. The spec for pull-down current is maximum of 150 A under worst case condition.
I/O Output Logic
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There are a maximum of eight global clock networks in each Eclipse-II device. Global clocks can drive logic cells and I/O registers, ECUs, and RAM blocks in the device. All global clocks have access to a Quad Net (local clock network) connection with a programmable connection to the logic cell's register clock input.
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Quad Net
Global Clock Net
GCLK Pin
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There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is local to a quadrant. Before driving the columns clock buffers, the quad-net is driven by the output of a mux which selects between the GCLK input and an internally generated clock source (see )LJXUH ).
Global Clock Network Internally generated clock, or clock from general routing network Global Clock (GCLK) Input FF
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There is one dedicated clock in the two larger devices of the Eclipse-II Family (QL8325 and QL8250). This clock connects to the clock input of the LogicCell and I/O registers, and RAM blocks through a hardwired connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global network with low skew. Users have the ability to select either the dedicated clock or the programmable clock ()LJXUH ).
Programmable Clock or General Routing Dedicated Clock
CLK
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Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be driven by the internal logic both as an I/O control or high drive. The performance of these drives is presented in 7DEOH .
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Eclipse-II devices are delivered with six types of routing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires supply VCC and GND (Logic `1' and Logic `0') to each column of logic cells. Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically used to implement intermediate length or medium fan-out nets.
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Express lines run the length of the programmable logic uninterrupted. Each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. The resistance will also be lower because the express wires don't require the use of "pass" links. Express wires provide higher performance for long routes or high fan-out nets. Distributed networks are described in the clock/control section. These wires span the programmable logic and are driven by "column clock" buffers. All clock network pin buffers (both Dedicated and Global) are hard wired to individual sets of column clock buffers.
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The Eclipse-II family of devices features a global power-on reset. This reset is hardwired to all registers and resets them to Logic `0' upon power-up of the device. In QuickLogic devices, the aynchronous Reset input to flip-flops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up. If you want to set the flip-flops to Logic `1', you must assert the "Set" signal after the Global POR signal has been deasserted.
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Power consumption of the two smaller Eclipse-II devices can be reduced significantly by deactivating the charge pumps inside the architecture. By applying 3.3 V to the Vpump pin, the internal charge pump is de-activated--this effectively reduces the dynamic power consumption of the device. Users who have a 3.3 V supply available in their system should take advantage of this low power feature by tying the Vpump pin to 3.3 V. Otherwise, if a 3.3 V supply is not available, this pin should be tied to ground.
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Tap Controller State Machine (16 States)
Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
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TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
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Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests:
* Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device.

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(FOLSVH,, )DPLO\ 'DWD 6KHHW 5HY % * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan
entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.
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* BSDL-Boundary Scan Description Language * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/ package combinations from QuickLogic * Extensive industry support available and ATVG (Automatic Test Vector Generation)
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There are two security links: one to disable reading logic from the array, and the second to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAMbased FPGAs. The option to program these fuses is selectable via QuickWorks in the Tools/Options/Device Programming window in SpDE.
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The flexibility link enables Power-Up loading of the Embedded RAM blocks. If the link is programmed, the Power Up Loading state machine is activated during power-up of the device. The state machine communicates with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would. The option to program this bit is selectable via QuickWorks in the Tools/Options/Device Programming window in SpDE. For more information on Power-Up Loading refer to QuickLogic Application Note 55.
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The DC Specifications are provided in 7DEOH through 7DEOH .
7DEOH $EVROXWH 0D[LPXP 5DWLQJV 3DUDPHWHU VCC Voltage VCCIO Voltage INREF Voltage Input Voltage Latch-up Immunity 9DOXH -0.5 V to 2.0 V -0.5 V to 4.0 V 0.5 V to VCCIO -0.5 V to VCCIO + 0.5 V 100 mA 3DUDPHWHU DC Input Current ESD Pad Protection Leaded Package Storage Temperature Laminate Package (BGA) Storage Temperature 9DOXH 20 mA 2000 V -65 C to + 150 C -55 C to + 125 C
7DEOH 2SHUDWLQJ 5DQJH 6\PERO 3DUDPHWHU 0LOLWDU\ 0LQ VCC VCCIO TA TC K Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature Delay Factor -7 Speed Grade -8 Speed Grade 1.71 1.71 -55 0.42 0.42 0D[ 1.98 3.60 125 1.35 1.27 ,QGXVWULDO 0LQ 1.71 1.71 -40 0.43 0.43 0D[ 1.98 3.60 85 1.26 1.19 &RPPHUFLDO 0LQ 1.71 1.71 0 0.46 0.46 0D[ 1.98 3.60 70 1.23 1.16 V V C C n/a n/a 8QLW
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7DEOH '& &KDUDFWHULVWLFV 6\PERO II IOZ CI CCLOCK IOS Ided IREF IPD 3DUDPHWHU I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitancea Clock Input Capacitance Output Short Circuit Currentb D.C. Supply Current on Vded D.C. Supply Current on INREF Current on programmable Pull-down &RQGLWLRQV VI = VCCIO or GND VI = VCCIO or GND Vo = GND Vo = VCC VCCIO = 3.6 V VCCIO = 2.5 V VCCIO = 1.8 V 0LQ -10 -15 40 -10 0D[ 10 10 8 8 -180 210 10 150 8QLWV A A pF pF mA mA mA A A
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b. Only one output at a time. Duration should not exceed 30 seconds.
7DEOH ,FF &KDUDFWHULVWLFV 'HYLFH QL8025 QL8050 QL8150 QL8250a QL8325a 9SXPS 2 mA 2 mA 9 9SXPS 9
a. For -7/-8 commercial grade devices only. Maximum ICC is 3 mA for all industrial grade devices and 5 mA for all military devices.
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7DEOH '& ,QSXW DQG 2XWSXW /HYHOVD ,15() 90,1 LVTTL LVCMOS2 LVCMOS18 GTL+ PCI SSTL2 SSTL3 n/a n/a n/a 0.88 n/a 1.15 1.3 90$; n/a n/a n/a 1.12 n/a 1.35 1.7 90,1 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 9,/ 90$; 0.8 0.7 0.63 INREF - 0.2 0.3 x VCCIO INREF - 0.18 INREF - 0.2 90,1 2.2 1.7 1.2 INREF + 0.2 0.5 x VCCIO INREF + 0.18 INREF + 0.2 9,+ 90$; VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.5 VCCIO + 0.3 VCCIO + 0.3 92/ 90$; 0.4 0.7 0.7 0.6 0.1 x VCCIO 0.74 1.10 92+ 90,1 2.4 1.7 1.7 n/a 0.9 x VCCIO 1.76 1.90 ,2/ P$ 2.0 2.0 2.0 40 1.5 7.6 8 ,2+ P$ -2.0 -2.0 -2.0 n/a -0.5 -7.6 -8
a. The data provided in 7DEOH and 7DEOH are JEDEC and PCI Specifications. QuickLogic devices either meet or exceed these requirements. For data specific to QuickLogic I/Os, see preceding 7DEOH through 7DEOH , )LJXUH through )LJXUH , and )LJXUH through )LJXUH .
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The AC Specifications (at VCC = 1.8 V, TA = 25 C, Worst Case Corner, Speed Grade = -7 (K = 1.16)) are provided from 7DEOH to 7DEOH . Logic Cell diagrams and waveforms are provided from )LJXUH to )LJXUH .
)LJXUH (FOLSVH,, Logic Cell
7DEOH /RJLF &HOOV 6\PERO /RJLF &HOOV tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low 3DUDPHWHU 0LQ 0.22 ns 0 ns 0.46 ns 0.46 ns 0.3 ns 0.3 ns 9DOXH 0D[ 0.257 ns 0.255 ns 0.18 ns 0.09 ns -
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7DEOH (FOLSVH,, &ORFN 'HOD\ &ORFN 6RXUFH 3DUDPHWHUV &ORFN 3HUIRUPDQFH *OREDO Logic Cells (Internal) Clock Pad Clock signal generated internally Clock signal generated externally 1.51 ns (max) 2.06 ns (max) 'HGLFDWHG 1.73 ns
7DEOH (FOLSVH,, *OREDO &ORFN 'HOD\ &ORFN 6HJPHQW 3DUDPHWHU 0LQ tPGCK tBGCK Global clock pin delay to quad net Global clock tree delay (quad net to flip-flop) 9DOXH 0D[ 1.34 ns 0.56 ns
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7DEOH 5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ 6\PERO 5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 3DUDPHWHU 0LQ 0.675 ns 0 ns 0.654 ns 0 ns 0.623 ns 0 ns 9DOXH 0D[ 4.38 ns
WCLK
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7DEOH 5$0 &HOO 6\QFKURQRXV DQG $V\QFKURQRXV 5HDG 7LPLQJ 6\PERO 5$0 &HOO 6\QFKURQRXV 5HDG 7LPLQJ tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD 3DUDPHWHU 0LQ 0.686 ns 0 ns 0.243 ns 0 ns 9DOXH 0D[ 4.38 ns
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new data
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old data
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Input register setup time: time the synchronous input of the flip-flop must be stable 2.50 ns before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-out: time taken by the flip-flop to output after the active clock edge -
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Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge
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7DEOH 6WDQGDUG ,QSXW 'HOD\V 6\PERO 6WDQGDUG ,QSXW 'HOD\V tSID (LVTTL) tSID (LVCMOS2) tSID (LVCMOS18) tSID (GTL+) tSID (SSTL3) tSID (SSTL2) 3DUDPHWHU 7R JHW WKH WRWDO LQSXW GHOD\ DGG WKLV GHOD\ WR W,68 LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V 0LQ 9DOXH 0D[ 0.34 ns 0.42 ns 0.68 ns 0.55 ns 0.61 ns
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Thermal Resistance Equations:
JC = (TJ - TC)/P JA = (TJ - TA)/P
PMAX = (TJMAX - TAMAX)/
JA
Parameter Description:
JC: Junction-to-case thermal resistance JA: Junction-to-ambient thermal resistance
TJ: Junction temperature TA: Ambient temperature P: Power dissipated by the device while operating PMAX: The maximum power dissipation for the device TJMAX: Maximum junction temperature TAMAX: Maximum ambient temperature
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Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75
Supply Voltage (V)
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Temperature Factor vs. Operating Temperature
1.15 1.10 1.05
Kt
1.00 0.95 0.90 0.85 -60
-40
-20
0
20
40
60
80
Junction Temperature C
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The basic power equation which best models power consumption is given below:
PTOTAL = 0.350 + f[0.0031 LC + 0.0948 CKBF + 0.01 CLBF+ 0.0263 0.543 RAM + 0.20 PLL+ 0.0035 INP + 0.0257 OUTP] (mW)
CKLD+
Where
* * * * * * * *
LC is the total number of logic cells in the design CKBF = # of clock buffers CLBF = # of column clock buffers CKLD = # of loads connected to the column clock buffers RAM = # of RAM blocks PLL = # of PLLs INP is the number of input pins OUTP is the number of output pins
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VCCIO
Voltage
VCC (VCCIO -VCC)MAX VCC
400 us
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The following requirements must be met when powering up a device (refer to )LJXUH ):
* When ramping up the power supplies keep (VCCIO -VCC)MAX 500 mV. Deviation from this
recommendation can cause permanent damage to the device. * VCCIO must lead VCC when ramping the device. * The power supply must be greater than or equal to 400 s to reach VCC. Ramping to VCC/VCCIO before reaching 400 s can cause the device to behave improperly.
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7DEOH -7$* 3LQ 'HVFULSWLRQV 3LQ TDI/RSI TRSTB/RRO TMS TCK TDO/RCO )XQFWLRQ Test Data In for JTAG/RAM init. Serial Data In Active low Reset for JTAG/RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG/RAM init. clock out 'HVFULSWLRQ Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Hold HIGH during normal operation. Connect to VCC if not used for JTAG Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization
IOCTRL(A)
VCCIO (A) INREF(A)
VCCIO (A) INREF(A)
IO(A)
IOCTRL(A)
IO BANK A VCCIO (H) INREF(H) IOCTRL(H) IO(H)
IO BANK B VCCIO (C) INREF(C) IOCTRL(C) IO(C)
IO BANK H
IO(A)
IO BANK C
IO BANK G
VCCIO (G) INREF(G) IOCTRL(G) IO(G)
VCCIO (D) INREF(D) IOCTRL(D) IO(D)
IO BANK D
IO BANK F
IO BANK E
INREF(E)
IO(E)
INREF(F)
IO(F)
VCCIO (E)
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7DEOH 'HGLFDWHG 3LQ 'HVFULSWLRQV 3LQ )XQFWLRQ 'HVFULSWLRQ Low skew global clock. This pin provides access to a dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. The I/O pin is a bi-directional pin, configurable to either an inputonly, output-only, or bi-directional pin. The A inside the parenthesis means that the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Connect to 1.8 V supply This pin provides the flexibility to interface the device with either a 3.3 V, 2.5 V, or 1.8 V device. The A inside the parenthesis means that VCCIO is located in BANK A. Every I/O pin in Bank A will be tolerant of VCCIO input signals and will output VCCIO level signals. This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V. Connect to ground Clock input for PLL Low skew global clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g. RAM, Flip Flops). Connect to GND The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in 7DEOH for the appropriate standard. The A inside the parenthesis means that INREF is located in BANK A. This pin should be tied to GND if not needed. Dedicated PLL output pin; otherwise, may be left unconnected This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a high-drive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. There is an internal pulldown resistor to Ground on this pin. This pin should be tied to Ground if it is not used. For backwards compatibility with Eclipse, it can be tied to Vcc or Ground. If tied to Vcc, it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor. 6KHHW RI
GCLK
Global clock network driver
I/O(A)
Input/Output pin
VCC
Power supply pin
VCCIO(A)
Input voltage tolerance pin
GND PLLIN DEDCLK GNDPLL
Ground pin PLL clock input Dedicated clock pin Ground pin for PLL
INREF(A)
Differential reference voltage
PLLOUT
PLL output pin
IOCTRL(A) Highdrive input
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Vpump
Charge Pump Disable
Vded
Voltage tolerance for clocks, JTAG, and IOCTRL/Voltage Drive for PLLOUT and JTAG pins
VccPLL
Power Supply pin for PLL
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All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint > Fix Placement in the Option pulldown menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in 7DEOH .
7DEOH 5HFRPPHQGHG 8QXVHG 3LQ 7HUPLQDWLRQV 6LJQDO 1DPH PLLOUTa 5HFRPPHQGHG 7HUPLQDWLRQ Unused PLL output pins must be connected to either VCC or GND so that their associated input buffer never floats. Utilized PLL output pins that route the PLL clock outside of the chip should not be tied to either VCC or GND. There is an internal pulldown resistor to Ground on this pin. This pin should be tied to Ground if it is not used. For backwards compatibility with Eclipse, it can be tied to Vcc or Ground. If tied to Vcc, it will draw no more than 20 A per IOCTRL pin due to the pulldown resistor. Any unused clock pins should be connected to VCC or GND. If a PLL module is not used, then the associated PLLRST must be connected to VCC, under normal operation use it as needed. If an I/O bank does not require the use of INREF signal the pin should be connected to GND.
IOCTRL
b
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a. x represents a number. b. y represents an aphabetical character.
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QL QuickLogic Device Part Number: 8025, 8050, 8150,8250, 8325 8050 -7 PQ208 C Operating Range: C = Commercial I = Industrial M = Military
Speed Grade: 7 Faster 8 Fastest Package Lead Count: PV100 = 100-pin VQFP PQ208 = 208-pin PQFP PT196 = 196-ball Chip Scale BGA (0.8 mm) PT280 = 280-ball FPBGA (0.8 mm) PS484 = 484-ball FPBGA (1.0 mm)
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Telephone: 408 990 4000 (US) 416 497 8884 (Canada) 44 1932 57 9011 (Europe) 49 89 930 86 170 (Germany) 852 8106 9091 (Asia) 81 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com support@quicklogic.com http://www.quicklogic.com/
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Copyright (c) 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
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